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ADSP-BF531 / ADSP-BF532 / ADSP-BF533
ELECTRICAL CHARACTERISTICS
400 MHz 1
500 MHz/533 MHz/600 MHz 2
Parameter
Test Conditions
Min
Typical
Max
Min
Typical
Max
Unit
V OH
High Level
V DDEXT = 1.75 V, I OH = –0.5 mA
1.5
1.5
V
Output Voltage 3 V DDEXT = 2.25 V, I OH = –0.5 mA
V DDEXT = 3.0 V, I OH = –0.5 mA
1.9
2.4
1.9
2.4
V
V
V OL
Low Level
V DDEXT = 1.75 V, I OL = 2.0 mA
0.2
0.2
V
Output Voltage 3 V DDEXT = 2.25 V/3.0 V,
0.4
0.4
V
I OL = 2.0 mA
I IH
High Level Input V DDEXT = Max, V IN = V DD Max
10.0
10.0
μA
Current 4
I IHP
High Level Input V DDEXT = Max, V IN = V DD Max
50.0
50.0
μA
Current JTAG 5
I IL6
Low Level Input V DDEXT = Max, V IN = 0 V
10.0
10.0
μA
Current 4
I OZH
Three-State
V DDEXT = Max, V IN = V DD Max
10.0
10.0
μA
Leakage
Current 7
I OZL6
Three-State
V DDEXT = Max, V IN = 0 V
10.0
10.0
μA
Leakage
Current 7
C IN
Input
f IN = 1 MHz, T AMBIENT = 25°C,
4
8 9
4
8 9
pF
Capacitance 8
V IN = 2.5 V
I DDDEEPSLEEP10 V DDINT Current in V DDINT = 1.0 V, f CCLK = 0 MHz,
Deep Sleep
T J = 25°C, ASF = 0.00
7.5
32.5
mA
Mode
I DDSLEEP
V DDINT Current in V DDINT = 0.8 V, T J = 25°C,
10
37.5
mA
Sleep Mode
SCLK = 25 MHz
I DD-TYP11
V DDINT Current
V DDINT = 1.14 V, f CCLK = 400 MHz,
125
152
mA
T J = 25°C
I DD-TYP11
V DDINT Current
V DDINT = 1.2 V, f CCLK = 500 MHz,
190
mA
T J = 25°C
I DD-TYP11
V DDINT Current
V DDINT = 1.2 V, f CCLK = 533 MHz,
200
mA
T J = 25°C
I DD-TYP11
V DDINT Current
V DDINT = 1.3 V, f CCLK = 600 MHz,
245
mA
T J = 25°C
I DDHIBERNATE10 V DDEXT Current in V DDEXT = 3.6 V, CLKIN = 0 MHz,
50
100
50
100
? A
Hibernate State T J = Max, voltage regulator off
(V DDINT = 0 V)
I DDRTC
V DDRTC Current
V DDRTC = 3.3 V, T J = 25 ° C
20
20
? A
I DDDEEPSLEEP
10
V DDINT Current in f CCLK = 0 MHz
6
Table 15
16
Table 14
mA
Deep Sleep
Mode
I DD-INT
V DDINT Current
f CCLK > 0 MHz
I DDDEEPSLEEP
I DDDEEPSLEEP mA
+ ( Table 17
? ASF)
+ ( Table 17
? ASF)
1
2
3
4
Applies to all 400 MHz speed grade models. See Ordering Guide on Page 63 .
Applies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. See Ordering Guide on Page 63 .
Applies to output and bidirectional pins.
Applies to input pins except JTAG inputs.
Rev. I
|
Page 22 of 64 |
August 2013
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